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Электронный компонент: HT1626

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HT1622
RAM Mapping 328 LCD Controller for I/O mC
Selection Table
HT162X
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4
4
8
8
8
8
16
16
16
SEG
32
32
32
32
48
64
48
64
64
Built-in Osc.
Crystal Osc.
1
April 21, 2000
General Description
HT1622 is a peripheral device specially de-
signed for I/O type mC used to expand the dis-
play capability. The max. display segment of
the device are 256 patterns (328). It also sup-
ports serial interface, buzzer sound, Watchdog
Timer or time base timer functions. The
HT1622 is a memory mapping and multi-func-
tion LCD controller. The software configuration
feature of the HT1622 make it suitable for mul-
tiple LCD applications including LCD modules
and display subsystems. Only three lines are
required for the interface between the host con-
troller and the HT1622. The HT162X series
have many kinds of products that match vari-
ous applications.
Features
Operating voltage: 2.7V~5.2V
Built-in RC oscillator
1/4 bias, 1/8 duty, frame frequency is 64Hz
Max. 328 patterns, 8 commons, 32 segments
Built-in internal resistor type bias generator
3-wire serial interface
8 kinds of time base/WDT selection
Time base or WDT overflow output
Built-in LCD display RAM
R/W address auto increment
Two selectable buzzer frequencies
(2kHz/4kHz)
Power down command reduces power
consumption
Software configuration feature
Data mode and Command mode instructions
Three data accessing modes
VLCD pin to adjust LCD operating voltage
Cascade application
Block Diagram
Pin Assignment
HT1622
2
April 21, 2000
S E G 1 2
N C
S E G 8
S E G 9
S E G 1 0
S E G 1 1
N C
S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
S E G 1 3
N C
N C
N C
N C
S E G 7
56
57
58
59
60
61
62
63
64
52
53
54
55
23
20
21
22
24
25
26
27
28
29
30
31
32
4 1
5 1
3 7
3 8
3 9
4 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
5 0
3 3
3 4
3 5
3 6
H T 1 6 2 2
- 6 4 Q F P
SEG
2
3
SEG
2
4
SEG
2
5
SEG
2
6
SEG
2
7
SEG
2
8
SEG
2
9
SEG
3
0
SEG
3
1
NC
SEG
2
0
SEG
2
1
SEG
2
2
C S
B Z
N C
R D
W R
D A T A
V S S
O S C I
V D D
V L C D
I R Q
N C
B Z
T 1
T 2
C O M 1
N C
T 3
C O M 0
CO
M
5
CO
M
2
CO
M
3
CO
M
4
CO
M
6
CO
M
7
SEG
0
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
SEG
6
1
1 1
2
3
4
5
6
7
8
9
1 0
1 2
1 3
1 4
1 5
1 8
1 9
1 6
1 7
W a t c h d o g T i m e r
a n d
T i m e B a s e G e n e r a t o r
D i s p l a y R A M
L C D D r i v e r /
B i a s C i r c u i t
C o n t r o l
a n d
T i m i n g
C i r c u i t
D A T A
W R
O S C I
C S
R D
C O M 0
C O M 7
S E G 0
S E G 3 1
T o n e F r e q u e n c y
G e n e r a t o r
B Z
B Z
I R Q
V S S
V D D
V L C D
Pad Assignment
Chip size: 149 155 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
HT1622
3
April 21, 2000
B Z
W R
R D
1
2 8
2
2 9
3
3 0
4
3 1
5
3 2
6
3 3
7
3 4
8
3 5
9
3 6
1 0
3 7
1 1
3 8
1 2
3 9
1 3
4 0
1 4
4 1
1 5
4 2
1 6
4 3
1 7
4 4
1 8
4 5
1 9
4 6
2 0
4 7
2 1
4 8
2 2
4 9
2 3
5 0
2 4
5 1
2 5
5 2
2 6
5 3
2 7
5 4
( 0 , 0 )
D A T A
V S S
O S C I
V D D
V L C D
B Z
T 1
T 2
T 3
C O M 0
C O M 1
C S
CO
M
2
CO
M
3
CO
M
4
CO
M
5
CO
M
6
CO
M
7
SE
G
0
SE
G
1
SE
G
2
SE
G
3
SE
G
4
SE
G
5
SE
G
6
S E G 7
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
SE
G
3
1
SE
G
3
0
SE
G
2
9
SE
G
2
8
SE
G
2
7
SE
G
2
6
SE
G
2
5
SE
G
2
4
SE
G
2
3
SE
G
2
2
SE
G
2
1
SE
G
2
0
I R Q
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
1
-68.43
71.78
28
48.15
-71.91
2
-68.43
59.46
29
54.78
-71.91
3
-68.43
52.83
30
69.32
-10.67
4
-69.19
39.14
31
69.32
-4.04
5
-69.36
23.89
32
69.32
2.59
6
-69.36
16.32
33
69.32
9.22
7
-69.36
9.69
34
69.32
15.85
8
-69.36
3.06
35
69.32
22.48
9
-69.36
-3.57
36
69.32
29.11
10
-69.36
-16.92
37
69.32
35.74
11
-69.36
-33.83
38
69.32
42.37
12
-69.36
-43.52
39
69.32
49.00
13
-69.36
-50.15
40
69.32
55.63
14
-69.36
-56.78
41
69.32
62.26
15
-69.36
-63.41
42
69.32
68.89
16
-69.36
-70.04
43
14.19
71.78
17
-39.23
-71.14
44
7.57
71.78
18
-32.60
-71.14
45
0.94
71.78
19
-20.19
-71.14
46
-5.70
71.78
20
-13.56
-71.14
47
-12.32
71.78
21
-1.15
-71.14
48
-18.95
71.78
22
5.48
-71.14
49
-25.58
71.78
23
15.00
-71.91
50
-32.22
71.78
24
21.63
-71.91
51
-38.85
71.78
25
28.26
-71.91
52
-45.47
71.78
26
34.89
-71.91
53
-52.10
71.78
27
41.52
-71.91
54
-58.74
71.78
HT1622
4
April 21, 2000
Pad Description
Pad No.
Pad Name
I/O
Description
1
CS
I
Chip selection input with Pull-high resistor. When the CS is logic
high, the data and command read from or written to the HT1622
are disabled. The serial interface circuit is also reset. But if CS is
at logic low level and is input to the CS pad, the data and com-
mand transmission between the host controller and the HT1622
are all enabled.
2
RD
I
READ clock input with Pull-high resistor. Data in the RAM of
the HT1622 are clocked out on the rising edge of the RD signal.
The clocked out data will appear on the data line. The host con-
troller can use the next falling edge to latch the clocked out data.
3
WR
I
WRITE clock input with Pull-high resistor. Data on the DATA
line are latched into the HT1622 on the rising edge of the WR sig-
nal.
4
DATA
I/O Serial data input/output with Pull-high resistor
5
VSS
Negative power supply, ground
6
OSCI
I
If the system clock comes from an external clock source, the ex-
ternal clock source should be connected to the OSCI pad.
7
VDD
Positive power supply
8
VLCD
I
LCD operating voltage input pad
9
IRQ
O Time base or Watchdog Timer overflow flag, NMOS open drain
output
10, 11
BZ, BZ
O 2kHz or 4kHz tone frequency output pair
12~14
T1~T3
I
Not connected
15~22
COM0~COM7
O LCD common outputs
23~54
SEG0~SEG31
O LCD segment outputs
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Storage Temperature.................-50C to 125C
Input Voltage................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature ..............-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-
mum Ratings may cause substantial damage to the device. Functional operation of this de-
vice at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
HT1622
5
April 21, 2000